The OTIS Reference Manual

This document describes the port definitions, electrical specifications, modes of operation and programming sequences of the OTIS TDC. The chip is developed for the Outer Tracker of the LHCb experiment. OTIS1.0 is the first full-scale prototype of this 32 channel TDC and has been submitted in April 2002 in a standard 0.25µm CMOS process. Within the clock driven architecture of the chip a DLL provides the reference for the drift time measurement. The drift time data of every channel is stored in the pipeline memory until a trigger decision arrives. A control unit provides memory and trigger management and handles data transmission to the subsequent DAQ stage. The latest chip version is OTIS1.3

Wafer test of the LHCb Outer Tracker TDC-Chip

The OTIS-TDC is the front end readout chip for the LHCb Outer Tracker. It is designed to measure drift times with a resolution better than 1 ns. As the chip will be directly mounted to its board, the test have to be performed on the wafer itself. As the testing period for 7 000 chips was only three weeks, many test routines have been implemented on a FPGA. Each chip is subjected to detailed probe testing to ensure the full functionality as well as a good performance. Overall 47 wafer have been tested. From the chips passing the test 2 000 have been used in the Outer Tracker front end electronic

Performance tests of an AGIPD 0.4 assembly at the beamline P10 of PETRA III

The Adaptive Gain Integrating Pixel Detector (AGIPD) is a novel detector system, currently under development by a collaboration of DESY, the Paul Scherrer Institute in Switzerland, the University of Hamburg and the University of Bonn, and is primarily designed for use at the European XFEL. To verify key features of this detector, an AGIPD 0.4 test chip assembly was tested at the P10 beamline of the PETRA III synchrotron at DESY. The test chip successfully imaged both the direct synchrotron beam and single 7.05 keV photons at the same time, demonstrating the large dynamic range required for XFEL experiments. X-ray scattering measurements from a test sample agree with standard measurements and show the chip's capability of observing dynamics at the microsecond time scale.Comment: revised version after peer revie

Development and test results of a readout chip for the GERDA experiment

This paper describes the F-CSA104 architecture and its measurement results. The F-CSA104 is for γ spectroscopy with Ge detectors. It is a low noise, fully integrated, four channel XFAB 0.6μm CMOS technology ASIC, that has been developed for the GERDA experiment. Each channel contains a charge sensitive preamplifier (CSA) followed by a 11.7MHz differential line driver. It has been particularly designed to operate in liquid argon (T = 87K/-186°C) and to have a measuring sensitivity of 660e- with an ENC of 110e-, after offline filtering with 10μs shaping, when connected to a 30pF load. Special techniques are used to improve the SNR such as a large input PMOS FET, an integrated 500MΩ CSA feedback resistor and a noise degeneration drain resistor

Enhanced Radiation Hardness and Faster Front Ends for the Beetle Readout Chip

This paper summarizes the recent progress in the development of the 128 channel pipelined readout chip Beetle, which is intended for the silicon vertex detector, the inner tracker, the pile-up veto trigger and the RICH detectors of LHCb. Deficiencies found in the front end of the Beetle Version 1.0 and 1.1 chips resulted in the submissions of BeetleFE 1.1 and BeetleFE 1.2, while BeetleSR 1.0 implements test circuits to provide future Beetle chips with logic circuits hardened against single event upset (SEU). Section I. motivates the development of new front ends for the Beetle chip, and section II. summarizes their concepts and construction. Section III. reports preliminary results from the BeetleFE 1.1 and BeetleFE 1.2 chips, while section IV. describes the BeetleSR 1.0 chip. An outlook on future test and development of the Beetle chip is given in section V

The LHCb Outer Tracker Front End Electronics

This note provides an overview of the front-end electronics used to readout the drift-times of the LHCb Outer Tracker straw tube chambers. The main functional components of the readout are the ASDBLR ASIC for amplification and signal digitization, the OTIS ASIC for the time measurement and for the L0 buffering, and the GOL ASIC to serialize the digital data for the optical data transmission. The L1 buffer board used to receive the data which is sent via the optical link is a common LHCb development and is not described here. This note supersedes an earlier document [1]

Development of a selftriggered high counting rate ASIC for readout of 2D gas microstrip neutron detectors

In the frame of the DETNI project a 32-channel ASIC suitable for readout of a novel 2D thermal neutron detector based on a hybrid low-pressure Micro-Strip Gas Chamber with solid 157Gd converter has been developed. Each channel delivers position information, a fast time stamp of 2 ns resolution and the signal amplitude (called energy below). The time stamp is used for correlating the signals from X and Y strips while the amplitude is used for finding the center of gravity of a cluster of strips. The timing and energy information are stored in derandomizing buffers and read out via token ring architecture